Phase change memory (PCM) technology such as multi-stack cross-point PCM is a promising alternative to other non-volatile (NV) memory technology, commonly known as non-volatile random access memory (NVRAM). Presently, reset current delivery has been a challenge in PCM memory technology due to high cell current requirement and high word line and bit line path resistance. The current mirror architecture used for reset current delivery has limited reset current delivery capability because the negative power supply of the reset current mirror may typically be set to be the inhibit voltage of the cross-point array, in order to avoid false selection of memory cells in the cross point array.